بررسی نویز فرکانس پایین از تک سلولی های  n-MOSFET برای برنامه های کاربردی حافظه
ترجمه نشده

بررسی نویز فرکانس پایین از تک سلولی های n-MOSFET برای برنامه های کاربردی حافظه

عنوان فارسی مقاله: بررسی نویز فرکانس پایین از تک سلولی های n-MOSFET برای برنامه های کاربردی حافظه
عنوان انگلیسی مقاله: Low frequency noise investigation of n-MOSFET single cells for memory applications
مجله/کنفرانس: بررسی نویز فرکانس پایین از تک سلولی های n-MOSFET برای برنامه های کاربردی حافظه
رشته های تحصیلی مرتبط: مهندسی برق
گرایش های تحصیلی مرتبط: مهندسی الکترونیک، توزیع و انتقال، الکترونیک قدرت، برق مخابرات
کلمات کلیدی فارسی: نویز فرکانس پایین، CMOS ،n-MOSFET ،Logic NVM
کلمات کلیدی انگلیسی: Low frequency noise، CMOS، n-MOSFET، Logic NVM
نوع نگارش مقاله: مقاله پژوهشی (Research Article)
شناسه دیجیتال (DOI): https://doi.org/10.1016/j.sse.2018.10.016
دانشگاه: Device and Process R&D, ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria
صفحات مقاله انگلیسی: 22
ناشر: الزویر - Elsevier
نوع ارائه مقاله: ژورنال
نوع مقاله: ISI
سال انتشار مقاله: 2019
ایمپکت فاکتور: 1/793 در سال 2017
شاخص H_index: 82 در سال 2019
شاخص SJR: 0/492 در سال 2017
شناسه ISSN: 0038-1101
شاخص Quartile (چارک): Q2 در سال 2017
فرمت مقاله انگلیسی: PDF
وضعیت ترجمه: ترجمه نشده است
قیمت مقاله انگلیسی: رایگان
آیا این مقاله بیس است: خیر
کد محصول: E11076
فهرست مطالب (انگلیسی)

Abstract

1- Introduction

2- Experiment

3- Results and discussion

4- Conclusions

References

بخشی از مقاله (انگلیسی)

Abstract

In this paper, we present a detailed investigation of low frequency noise (LFN) for different n-MOSFET devices dedicated for memory applications. We investigate the impact of the gate oxide thickness (GOX) on LFN. We analyzed how the position, the existence and the composition of Lightly Doped Dopant (LDD) implant in the source/drain region affect the LFN performance of the device. The results demonstrates that the thinner gate oxide and the device without LDD improved the noise performance compared the devices with thick GOX and with LDD implants. On the other hand, the absence of LDD implant on one side of the MOSFET didn’t reveal a global trend for all measured devices. Finally, the different LDD implant composition resulted in different LFN performance which is gate area dependent. These results can be used from both process and design engineers to improve the LFN of n-MOSFET.

Introduction

Today, it is well known that LFN can be used as a characterization tool for the quality and the reliability of the devices [1-2]. It is obvious that the level of noise has a direct impact on the device quality. In addition, LFN can influence the design of an electronic circuit since it can limit the overall performance and operation. Thus, the noise investigation of special architecture devices is of paramount importance for device and design engineers. Single transistors designed for logic NVM of SONOS type memory applications [3] can be used for LFN comprehension analysis due to the special architecture they have. In this experiment five single cell n-MOSFET devices were designed for memory applications and used for noise analysis. In literature exists a number of publications referring to LFN characterization for logic NVM of SONOS type [4-7]. According to our knowledge, we could not find a prior work that used these type of devices for LFN improvement purposes and not for simple characterization. We tried not only to identify the main source of LFN in these devices but also to use this info for the improvement of LFN performance in CMOS technology. In MOSFETs, it is generally accepted that the flicker (1/f-like) noise originates either from carrier number fluctuations (CNF) (Eques 1, 2 Table 1) [1] or from Hooge mobility fluctuations [8]. The CNF noise is due to carrier exchange between the near-interface gate dielectric traps and the channel. The charge fluctuations in the gate dielectric could also induce fluctuations of the carrier mobility, giving rise to the so-called correlated mobility fluctuations (CMF) (Eques 3, 4 Table 1) [9-11].