دانلود مقاله پیاده سازی FPGA قابل تنظیم شبکه های عصبی
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دانلود مقاله پیاده سازی FPGA قابل تنظیم شبکه های عصبی

عنوان فارسی مقاله: پیاده سازی FPGA قابل تنظیم شبکه های عصبی
عنوان انگلیسی مقاله: Reconfigurable FPGA implementation of neural networks
مجله/کنفرانس: محاسبات عصبی – Neurocomputing
رشته های تحصیلی مرتبط: مهندسی کامپیوتر
گرایش های تحصیلی مرتبط: هوش مصنوعی
کلمات کلیدی فارسی: شبکه های عصبی، FPGA
کلمات کلیدی انگلیسی: FPGA; Neural networks
نوع نگارش مقاله: مقاله کوتاه (Short Communication)
شناسه دیجیتال (DOI): https://doi.org/10.1016/j.neucom.2018.04.077
دانشگاه: Rzeszów University of Technology – ul. Powstańców Warszawy – Poland
صفحات مقاله انگلیسی: 18
ناشر: الزویر - Elsevier
نوع ارائه مقاله: ژورنال
نوع مقاله: ISI
سال انتشار مقاله: 2018
ایمپکت فاکتور: 5.188 در سال 2018
شاخص H_index: 110 در سال 2019
شاخص SJR: 0.996 در سال 2018
شناسه ISSN: 0925-2312
شاخص Quartile (چارک): Q1 در سال 2018
فرمت مقاله انگلیسی: PDF
وضعیت ترجمه: ترجمه نشده است
قیمت مقاله انگلیسی: رایگان
آیا این مقاله بیس است: خیر
کد محصول: E8627
فهرست مطالب (انگلیسی)

Abstract

1- Introduction

2- Resources-saving implementation

3- Parallel implementation

4- Resources requirement, calculations speed and accuracy

5- Conclusions

References

بخشی از مقاله (انگلیسی)

Abstract 

 This brief paper presents two implementations of feed-forward artificial neural networks in FPGAs. The implementations differ in the FPGA resources requirement and calculations speed. Both implementations exercise floating point arithmetic, apply very high accuracy activation function realization, and enable easy alteration of the neural network's structure without the need of a re-implementation of the entire FPGA project.

Introduction

Most of the existing artificial neural networks (ANNs) applications, particularly for commercial environment, are developed as software. Yet, the parallelism offered by hardware may deliver some advantages such as higher speed, reduced cost, and higher tolerance of faults (graceful degradation) [1, 2]. Among various developed methods of ANNs implementations in field programmable gate arrays (FPGAs), e.g., [3 - 6], there is a breed of implementation which allows the structure of the ANN (i.e., the number of layers and/or neurons, etc.) to be altered without the need of re-synthesizing and re-implementation of the whole FPGA project. This feature increases the ANNs implementation flexibility to the similar level as offered by software, at the same time maintaining the advantages delivered by hardware. Unfortunately, existing solutions, e.g., [7 - 9], are based on fixed point arithmetic, have strongly limited calculations accuracy of the activation function, and require dedicated software tools for the formulation of a set of user instructions controlling the ANN calculations in the developed hardware. Some of them [9, 10] do not employ parallel architecture exploiting only a single neuron block for the calculations of the whole ANN. In the case of [10] floating point (FP) arithmetic is used and a relatively high accuracy of the activation function is achieved, however the feasibility of the alteration of the ANN structure without reimplementation of the whole project is heavily compromised