تحلیل قابلیت کنترلر ربات مبتنی بر تحمل پذیری خطای مدار مجتمع دیجیتال
ترجمه نشده

تحلیل قابلیت کنترلر ربات مبتنی بر تحمل پذیری خطای مدار مجتمع دیجیتال

عنوان فارسی مقاله: تجزیه و تحلیل قابلیت اطمینان گسترده کنترلر ربات مبتنی بر تحمل پذیری خطای مدار مجتمع دیجیتال برنامه پذیر
عنوان انگلیسی مقاله: Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller
مجله/کنفرانس: Latin American Test Symposium
رشته های تحصیلی مرتبط: برق، کامپیوتر
گرایش های تحصیلی مرتبط: هوش مصنوعی، مهندسی نرم افزار، الکترونیک، مدارهای مجتمع الکترونیک، برنامه نویسی کامپیوتر، مهندسی کنترل، ماشین های الکتریکی
کلمات کلیدی فارسی: تجزیه و تحلیل قابلیت اطمینان، TMR، مدار مجتمع دیجیتال برنامه پذیر، تحمل پذیری خطا، کنترلر ربات
کلمات کلیدی انگلیسی: Reliability Analysis، TMR، FPGA، Fault Tolerance، Robot Controller
شناسه دیجیتال (DOI): https://doi.org/10.1109/LATW.2019.8704554
دانشگاه: Faculty of Information Technology, Brno University of Technology, Centre of Excellence IT4Innovations, Brno, 612 66, Czech Republic
ناشر: آی تریپل ای - IEEE
نوع ارائه مقاله: کنفرانس
نوع مقاله: ISI
سال انتشار مقاله: 2019
شناسه ISSN: 2373-0862
فرمت مقاله انگلیسی: PDF
تعداد صفحات مقاله انگلیسی: 4
وضعیت ترجمه: ترجمه نشده است
قیمت مقاله انگلیسی: رایگان
آیا این مقاله بیس است: خیر
آیا این مقاله مدل مفهومی دارد: ندارد
آیا این مقاله پرسشنامه دارد: ندارد
آیا این مقاله متغیر دارد: دارد
کد محصول: E13312
رفرنس: دارای رفرنس در داخل متن و انتهای مقاله
فهرست انگلیسی مطالب

Abstract


I- Introduction


II- Reliability Analysis and its Improvement


III- Evaluation Platform and Experimental System


IV- Reliability Analysis and Experimental Evaluation


V- Conclusions and Future Research


References

نمونه متن انگلیسی مقاله

Abstract


The reliability of safety-critical systems is very important especially in case of electronic systems which are working in environment with increased occurrence of faults. As an example, space, aerospace or medical systems can serve. Fault tolerance is one of the techniques the goal of which is to avoid the impact of faults on such systems. Lots of fault tolerance techniques exists and new ones are under investigation. This paper is targeted mainly to Field Programmable Gate Arrays (FPGAs) which are also the target technology of many fault tolerant techniques. It is important to evaluate and test these techniques. This paper is the continuation of our previously published research results which presents experimental approach to evaluate such fault tolerance techniques by monitoring the impact of faults in the experimental electro-mechanical system utilizing robot navigation in a maze. However, in this paper, we research and compare similarities of the theoretical estimation to various methods of the SEU injection approaches. The theoretical estimation is calculated using known equations. The impact of artificially faults injected into the electronic controller, in which Triple Modular Redundancy is applied, is monitored and used for statistic reliability analysis. This approach serves as a tool for the fast reliability evaluation during the development process of fault tolerance systems.


INTRODUCTION


The reliability of safety-critical electronic systems which are working in environment with increased occurrence of faults is a very challenging topic. A technique called fault tolerance [1] is commonly used technique which makes electronic systems more reliable. The goal of this approach is to keep the system functional, even in the presence of faults. It means that fault tolerance accepts the fact a fault can appear in electronic system. Various types of redundancy are the core of such techniques. Hardware and time redundancy are the most common ones. Combination and improvements of these basic methods are still under investigation, e.g. authors of [2] present approach which is based on the combination of hardware and time redundancies. Many fault-tolerant methodologies targeted to Field Programmable Gate Arrays (FPGAs) have been developed and new ones are under investigation [3]. The main reason is that FPGAs are more popular thanks to their flexibility and ability to be reconfigured in case of fault occurrence. Sensitivity of FPGAs to faults caused by charged particles [4] is the problem from the reliability point of view. The configuration of FPGA is stored as a bitstream in SRAM memory and charged particle can cause inversion of bit in the bitstream. This event is called Single Event Upset (SEU) [5].

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