Transient overvoltage and inrush current are two major transient phenomena which occur because of capacitor switching. In addition to power quality degradation, these transients lead to shortening the lifetime of the capacitor and switching device. In order to reduce these transients, a solid-state capacitor switching transient limiter (SSCSTL) is proposed in this study. The proposed SSCSTL has two operation modes: limiting mode and bypass mode. During the capacitor energising, a DC reactor and a varistor suppress inrush current and transient overvoltage, respectively. During the steady-state mode, the DC reactor is bypassed by a thyristor, so the SSCSTL acts as short-circuit and has no considerable effect on the circuit. The thyristor is triggered by using a new simple structure auto-triggering technique in normal condition. The proposed SSCSTL with a very simple structure as well as fast and reliable performance is an efficient solution to assure the capacitor switching without any transient overvoltage and inrush current. A prototype single-phase SSCSTL is simulated by electromagnetic transient program and tested. The simulation and experiment results show that the proposed SSCSTL considerably reduces the inrush current and transient overvoltage during switching of the capacitor.
Power capacitor banks are widely used to improve the power factor in power systems. Closed to unity power factor has several advantages such as loss reduction in the distribution feeders, capacity increase of transmission lines and transformers, as well as the desired voltage profile. Owing to the continuous variation of the inductive loads in the power systems, capacitor banks should be switched on/off frequently by an automatic power factor regulator according to the required power factor in the substations or industrial plants . However, transient overvoltage and inrush current arise in capacitor switching condition . In addition to power quality degradation, such transients lead to a decrease in the lifetime of the capacitor and switching device. So, some standards have been recommended regarding the capacitor bank switching [3, 4]. Furthermore, several approaches have been proposed to restrain the capacitor switching transients, which are generally based on two concepts: increase the line impedance at the switching instant or close the switch contacts when the voltage across the contacts is zero. In , a series current limiting reactor is proposed to limit the capacitor switching transients. This method is simple and inexpensive, but a fixed reactor may cause system resonance. Therefore an increased voltage rating of the capacitor bank may be required when this technique is utilised. Pre-insertion resistor/inductor is another approach, suggested in [5, 6]. Zero-voltage switching of the switch contacts [7, 8] and power electronic control-based techniques [9–12] are other alternatives. These approaches require an additional control circuit, which leads to an increase in the cost and complexity. Furthermore, they are less reliable.
In this paper an efficient solid-state capacitor switching transient limiter (SSCSTL) is proposed for restriction of the capacitor switching transients. Upon switching, the SSCSTL goes to transient supersession mode so that a DC reactor limits the switching inrush current, and switching transient overvoltage is clamped by means of a varistor. After energisation of the capacitor bank, the SSCSTL goes to bypass mode and a thyristor (Th) bypasses the DC reactor, so the SSCSTL acts as a short-circuit path. Consequently, the SSCSTL has no effect on the circuit in steady state. The SSCSTL has a fast response time for switching between the limiting and bypass modes, which is <20 ms. It uses a simple and reliable auto-triggering circuit for energising the capacitor bank. As a result of the utilisation of a DC-type reactor, there is no concern about the series resonance. In addition to suppression of the capacitor switching transients, the SSCSTL limits the fault current in case of a fault occurrence in the capacitor bank.
The rest of the paper is organised as follows: in Section 2, configuration of the SSCSTL and its operation principles are presented. Section 3 develops the circuit analysis of the proposed limiter. In Section 4, performance of the SSCSTL is evaluated by using some simulation and experimental results. Finally, in Section 5 the results are concluded.
2 SSCSTL structure and its operation principle
A single-phase topology of the SSCSTL is considered to demonstrate its operation principle. However, it can be straightforwardly extended to a three-phase structure. In this section, the structure of the proposed capacitor switching transient limiter is presented. Furthermore, duties of different parts of the SSCSTL are introduced. Finally, the SSCSTL operation modes will be discussed.
2.1 SSCSTL structure
The circuit structure of the SSCSTL is shown in Fig. 1. Its structure can be divided into two sections: power section and control section. The power section is composed of a DC reactor (L), an external resistance (RE), a single-phase bridge rectifier or power rectifier (D1–D4), a Th and a high-power varistor (MOV1). The control section includes a low-power transformer (T), a single-phase rectifier with low-power centre-tap transformer or control rectifier (Da and Db), and a voltage regulator (L7805). The DC reactor is connected to the DC side of the power rectifier, connected in parallel with a Th, series resistor-capacitor (RC) snubber components (Rs and Cs) and a varistor (MOV2). In order to prevent core saturation in the DC reactor and reduce the remnant flux, the inductor core can be designed with an air gap. The inductor limits the inrush current of the capacitor switching. The varistor (MOV2) and series RC components protect the Th against transient overvoltage switching. Operation voltage of MOV2 is selected higher than the maximum of the supply voltage. The Th bypasses the inductor and snubber components in steady-state condition. A varistor (MOV1) is also considered for transient overvoltage suppression of the capacitor switching. Operation voltage of MOV1 is selected slightly higher than the operation voltage of MOV2.
In the control section, a low-power 220/9 V transformer is connected in parallel with the capacitor bank. A single-phase rectifier with low-power centre-tap transformer feeds the trigger circuit. The regulator (L7805) is considered to protect the Th against overvoltage in gate cathode.
2.2 SSCSTL operation principle
Essential limiting elements of the proposed SSCSTL are a DC reactor/MOV varistor placed in series/parallel with the capacitor bank, respectively. Transient overvoltage during switching is suppressed by the MOV. Transient overcurrent is limited by the DC reactor. Accordingly, the proposed SSCSTL has two operation modes: limiting mode and bypass mode. In the limiting mode (during initial moments after the capacitor switching), capacitor voltage and secondary voltage of T are less than the required voltage for driving the Th. So, Th remains off and the DC reactor and external resistor limit the inrush current of the capacitor bank. In addition, the switching transient overvoltage is suppressed by the varistor MOV1. In the bypass mode (after appropriate voltage build-up across the capacitor bank), secondary voltage of transformer T reaches a sufficient level, which turns-on the Th and so the DC reactor will be bypassed. In fact, the capacitor bank current passes through the Th and D1–D4, which forms a short-circuit path. The centre-tap rectifier and regulator L7805 are used for driving the Th.
The limiting and bypassing modes of the proposed SSCSTL can be categorised in two states of operation, which are described in the following section.