This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of 0.12 mm . Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving.
I. INTRODUCTION MODERN
communication systems require data rates up to several tens of Gb/s. One particularly challenging case is the wireless board-to-board communication in supercomputers, where data throughput above 100 Gb/s is needed. Technically this can be achieved with carrier frequencies above 100 GHz, as large bandwidths up to tens of GHz are available in this case . Systems with such large bandwidth are very challenging for the incorporated analog-to-digital converters (ADCs), which can easily become the bottleneck of the wireless link. Additionally, in order to enable systems-on-chip (SOCs) with digital signal processing and ADCs integrated on the same chip, it becomes a requirement for the ADC to be realized in a modern CMOS technology. Recently published CMOS ADCs show good power efficiency at sampling rates in the lower GHz range – with successive approximation register (SAR) ADCs being most popular. It is possible to reach higher sampling rates with the same basic circuit structures by applying time interleaving –. As long as the overhead of multi-phase clock generation is negligible, it is theoretically possible to increase the sampling rate with no penalty in terms of required energy per conversion. For this reason time-interleaving topologies are widely used for high-speed ADCs and have been “extensively exploited to achieve low figures of merit” , equivalent to low energy per conversion step in this context. Recently, sampling rates as high as 90 GS/s have been reported with ADC cores running at 1.4 GS/s . Unfortunately it is not possible to use time interleaving at an arbitrary scale, as several problems limit the performance of heavily interleaved systems, such as jitter in multi-phase clock generation and distribution, clock transition times, input capacitance, requirements on the track-and-hold amplifiers (THAs), and latency , –. Further increases in sampling rate without exacerbating those problems can be achieved by implementing faster ADC cores. This relaxes the requirements on the multi-phase clock generation and reduces the latency, while enabling highest input bandwidth.
The design goal for the presented ADC has been to achieve the highest possible sampling speed with a single ADC core. As a result, the flash ADC topology has been chosen. The presented ADC core is capable of working at sampling rates up to 24 GS/s , while being designed in a low-cost low-power digital CMOS technology. In addition to the topics presented in , this paper presents comprehensive design considerations for the analog input stages and gives insights into the circuit implementation of all ADC sub-blocks. Furthermore, it shows additional and more detailed measurement results, statically as well as at highest input frequencies. Section II shows the ADC architecture. As circuit implementations for such high frequencies require comprehensive design considerations, it is important to specify the bandwidth requirements for the critical circuit blocks, especially for the analog input stages. Section III investigates the track-and-hold (T/H) circuit and the subsequent buffer stage and provides a method to directly calculate the required bandwidth without extensive circuit simulations. Insights into the circuit implementation are given in Section IV, while Section V presents the chip characterization.
II. ADC ARCHITECTURE
Fig. 1 shows the system-level schematic of the presented ADC. For highest conversion speed, it relies on the flash topology. The schematic shows a T/H stage and subsequent buffer at the input, followed by a comparator (Cmp), further amplifiers, and latches (L) in each of the parallel data-processing paths. The binary output signals are generated by thermometer to binary conversion logic (T2B). By utilizing a modern CMOS process it is possible to achieve sampling rates of tens of GHz with circuit structure sizes in the range of hundreds of m. This requires RF design techniques including electromagnetic (EM) field simulations for lines and structures because the circuit size is no longer negligible. Special care needs to be taken of the bandwidth of the analog frontend consisting of the T/H buffer and the comparators. The time synchronization after the comparators is usually performed by a master–slave flip-flop, which is very challenging to design at frequencies of tens of GHz. In order to reduce the effective regeneration time, three latches and an amplifier have been combined to form a master–slave–master (MSM) flip-flop .
III. BANDWIDTH CONSIDERATIONS
Circuit operation at highest speed requires careful bandwidth consideration. The input stages consisting of a T/H circuit and subsequent buffer pose the highest requirements because they work in the analog domain where the signals contain time and amplitude information. While it is a common approach to determine the required bandwidth by complex transistor-level simulations, this section presents practical equations based on simple models to directly calculate the target bandwidth.
A. T/H Stage
The most basic topology of a switched capacitor (SC) T/H circuit is shown in Fig. 2(a). The transistor controls the electrical connection between the input and output of the circuit. While input and output are isolated during the hold phase and the charge on the hold capacitor is preserved, the electrical connection during the track phase should ideally be a short circuit. In this phase the impedance between input and output depends on the drain–source resistance of , which can be modeled as a resistor .
This creates a first-order low-pass filter as a simple model for a SC T/H circuit in track mode, as illustrated in Fig. 2(b). For input frequencies close to the Nyquist frequency it is possible that two consecutive hold voltages are at the minimum and at the maximum of the input signal envelope. In this case the output signal of the T/H stage has to change from the minimum value to the maximum within one tracking period. This scenario can be modeled with a step at the input of the T/H stage with the amplitude , the peak-to-peak value of the T/H input voltage. The corresponding step response converges exponentially towards the input step value with a time constant of , as shown in Fig. 3,
B. T/H Buffer
Apart from designing the T/H stage it is also important to consider the bandwidth of the subsequent buffer. High bandwidth is difficult to achieve for this buffer because it has to drive all comparators, which create a large capacitive load. On the other hand, this buffer is especially important because if its bandwidth is too low it will substantially decrease the effective ADC resolution, as has been described in . While in other designs this critical point is addressed empirically and only sometimes the resulting bandwidth specifications are given , this section describes a method to calculate the bandwidth requirements for the T/H buffer, which can be used for system-level specifications without extensive circuit simulation.